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NJU3426
PRELIMINARY
16-SEGMENT X 15-Digit VFD CONTROLLER / DRIVER
! GENERAL DESCRIPTION
The NJU3426 is a VFD (Vacuum Fluorescent Display) controller/driver to dynamically drive up to 16 segments x 15 digits. It consists of display data RAM, an address counter, command registers, a serial interface and high voltage drivers. The direct control from the MPU and high voltage drivers of 45V make the NJU3426 well suited for various VFD displays.
! PACKAGE OUTLINE
NJU3426FP1
! FEATURES
# # # # # # # # # # # # Directly Drives 16-segment x 15-digit High VFD Driving Voltage : |VDD-VFDP|=45V Display Shift Function Programmable Duty Ratio for Timing Signal :2/16, 4/16, 6/16, 8/16, 10/16, 12/16, 14/16, 15/16 duty Display ON/OFF Control Function Display Data RAM : 30 x 8-bit Built-in Oscillator (Formed by Connecting an External Ceramic Resonator) 8-bit Serial Interface Power-ON Reset Function Operating Voltage :3.0 to 5.5V C-MOS Technology Package Outline :QFP48-P1 S0 to S15 T0 to T13
! BLOCK DIAGRAM
VDD VSS VFDP
High Voltage Driver
High Voltage Driver
Segment Data Latch
Timing Counter
Character Address Counter
Address Counter
Display RAM 30 x8-bit
Initial Character Address Counter
Duty Counter
Timing Counter
OSC Instruction Decoder
XT XTb
SI SCK CSb
Serial Buffer
REST
RSTb
02/08/29 -1-
NJU3426
! FUNCTION DESCRIPTION
(1) ADDRESS COUNTER The address counter indicates the "Display data RAM address", in which the display data will be transferred and stored. For the data transmission, once an initial RAM address is determined, the display data can be continuously transmitted without setting the RAM address each time. When the upper 2 bits (B7 and B6) of the 1st word are "0,0", the lower 5 bits (B4 to B0) are recognized as RAM address data. And, the 2nd word is recognized as display data, which will be stored in the RAM address designated by the 1st word, and simultaneously the RAM address is counted up by an auto-increment operation. The "Display data RAM address", which can be specified by the 1st word, ranges from "0,0,0,0,0" (00H) to "1,1,1,0,1" (1DH). However, the auto-increment keeps counting up to "1,1,1,1,1" (1FH) every display data transmission because of the 5-bit address counter, and finally the RAM address wraps to "0,0,0,0,0" (00H) and begins counting up. Note that the display data, stored in the RAM address of "1,1,1,1,0" (1EH) and "1,1,1,1,1" (1FH), is ignored in this sequence. DISPLAY DATA RAM ADDRESS B7 0 B6 0 B5 * B4 AD4 B3 AD3 B2 AD2 B1 AD1 B0 AD0
Recognition data
Display data RAM address *:don't care
Character address
B7
B6
B5
B4
B3
B2
B1
B0
RAM Address
B7
B6
B5
B4
B3
B2
B1
B0
RAM Address
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 S15 S14 S13 S12 S11 S10 S9 S8
01H 03H 05H 07H 09H 0BH 0DH 0FH 11H 13H 15H 17H 19H 1BH 1DH 1FH S7 S6 S5 S4 S3 S2 S1 S0
00H 02H 04H 06H 08H 0AH 0CH 0EH 10H 12H 14H 16H 18H 1AH 1CH 1EH
: These display data is ignored. DISPLAY DATA RAM MAPPING
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NJU3426
(2) COMMAND REGISTER 1 The "Command register 1" is used for setting "Duty ratio for timing signal", "Display control ON/OFF" and "Shifting display digits". When the upper 1 bit (B7) of the 1st word is "1", the lower 7 bits (B6 to B0) are recognized as command data, and stored in the "Command register 1". Note that changing the "Duty ratio" or "Shifting display digits" must be executed under the "Display control OFF", otherwise it may cause flickering. The contents of the "Command register 1" is initially set up at power-ON reset or reset signal, as shown below. DEFAULT VALUES OF COMMAND REGISTER 1 * Duty ratio for timing signal : 2/16 * Display control ON/OFF : OFF * Shifting display digits :7 B7 1 B6 DT2 B5 DT1 B4 DT0 B3 DSP B2 DE2 B1 DE1 B0 DE0
Recognition data
Duty ratio for timing signal
Display control ON / OFF
Shifting display digits
MD2 0 0 0 0 1 1 1 1
MD1 0 0 1 1 0 0 1 1
MD0 0 1 0 1 0 1 0 1
Duty ratio for timing signal 2/16 4/16 6/16 8/16 10/16 12/16 14/16 15/16
Note.)
DSP Display control 0 OFF 1 ON When the "Display control is OFF" is set, all output pins become in display OFF state. DE2 0 0 0 0 1 1 1 1 DE1 0 0 1 1 0 0 1 1 DE0 0 1 0 1 0 1 0 1 Shifting display digits 7 8 9 10 11 12 13 14
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NJU3426
(3) COMMAND REGISTER 2 The "Command register 2" is used for setting the "Initial character address" , which corresponds to the T0 pin. When the upper 2 bits (B7 and B6) of the 1st word is "0,1", the lower 4 bits (B3 to B0) are recognized as command data, and stored in the "Command register 2". The contents of the "Command register 2" is initially set up at power-ON reset or reset signal, as shown below. DEFAULT VALUES OF COMMAND REGISTER 2 * Initial character address : C1 (0,0,0,1) B7 0 B6 1 B5 * B4 * B3 DS3 B2 DS2 B1 DS1 B0 DS0
Recognition data
Initial character address *:don't care
DS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
DS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
DS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
DS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Initial character address C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 Prohibited
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NJU3426
(4) DISPLAY SHIFT OPERATION The display shift operation can be performed by changing the "Initial character address" of the "Command register 2". And, the number of digits for the display shift in the loop is determined by the "Shifting display digits" of the "Command register 1". In other words, shifting display area ranges from the "Initial character address" specified by the "Command register 2" to the last address designated by the "Command register 1". The default value of the "Initial character address" is C1 (0,0,0,1), as shown in the table of "Display data RAM". In addition, supposing that the value of the "Shifting display digits" is "N", the "Initial character address" must be set in the range between C0 and CN in order not to exceed the digit "N". Because the display shift operation doesn't apply to the addresses beyond the range of the digit "N", the display images, initially set, appear on these addresses. Just for reference, one character of display image is composed of 16 segments. HOW TO SET LEFT DISPLAY SHIFT The left display shift is carried out by incrementing the "Initial character address" gradually like C2, C3, C4, --CN. To the contrary, decrementing the address performs right display shift. The following description provides the example on how to set the left display shift, using alphanumeric display images such as "0", "1", "2", ---, "9", "A", "B", ---, and "E". STEP1) Setting display images in the display data RAM
*
Display RAM data Character address Display image
C0 0
C1 1
C2 2
C3 3
C4 4
C5 5
C6 6
C7 7
C8 8
C9 C10 C11 C12 C13 C14 9 A B C D E
SETP2) Setting the "Initial character address" to C2 and the "Shifting display digits N" to 12 (T11). Shifting display digits
Character address Timing output terminals Character Display image
C1
C2
C3
C12
C0
C13
C14
T0 1
T1 2
T10 11
T11 12
T12 13
T13 14
is not shifted. In this setting, the display images of "2", "3",- - - appear on the T0, T1, T2, - - - T10 pins respectively, and the image "0" is on the T11 pin, which is assigned to the 12th character address. The display images "D" and "E" don't shift but remain on the T12 and T13 pins, assigned to the 13th and 14th characters respectively, because their character addresses are outside of the digit "N". STEP3) Changing the "Initial character address" to C3, and leaving the "Shifting display digits N" as 12 (T11). Shifting display digits
Character address Timing output terminals Character Display image
C2
C3
C4
C0
C1
C13
C14
T0 1
T1 2
T10 11
T11 12
T12 13
T13 14
is not shifted.
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NJU3426
! TIMING SIGNAL / DUTY-CHANGE WAVEFORM
Display timing
13 14 15 ST2 ST1 ST0 01 2345 678 9 10 11 12 13 14 15 01 2 3 456
(Duty count)
2/16 4/16 6/16 8/16 10/16 12/16 14/16 15/16
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Timing signal (T0 to T14)
Segment signal
! DISPLAY TIMING CHART
fXT XT tBK T0 T1 T2 * * * * T13 tSP * * * * tDG
S0 to S15
Oscillation frequency Minimum blanking time (duty15/16) 1-character display time 1-cycle display time
: fXT : tBK=(1/fXT) x 16 x 2 : tDG=tBK x 16 : tSP=tDG x 14
:800kHz to 3.5MHz :40s to 9.2s :640s to 147.2s :20.608ms to 8.96ms
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NJU3426
(5) SERIAL DATA TRANSMISSION Communication between the NJU3426 and MPU uses the serial data transmission with synchronous clock, and 8 bits serial data constitutes 1 word. Each bit on the SI pin is fetched at the rising edge of the serial clock (SCK), and the entire 8 bits are loaded as 1 word at the rising edge of the chip select (CSb). During one communication, multiple words can be transferred continuously. The 1st word must be either "Display data RAM address", "Command register 1" or "Command register 2". When the 1st word is RAM address data, the 2nd and ascending words must be display data. When it's the "Command register 1 or 2", the 2nd and ascending words are ignored. SCK
SI
D0
D1
D2
D3
D4
D5
D6
D7
SERIAL DATA TIMING
CSb
SCK
SI
WORD 1
WORD 2
WORD n
SERIAL DATA TRANSMISSION FORMAT
*
Serial input data ST DATA FORMAT FOR THE 1 WORD DISPLAY DATA RAM ADRESS B7 0 B6 0 B5 * B4 AD4 B3 AD3 B2 AD2 B1 AD1 B0 AD0 *:don't care COMMAND DATA 1 B7 1 B6 DT2 B5 DT1 B4 DT0 B3 DSP B2 DE2 B1 DE1 B0 DE0 *:don't care COMMAND DATA 2 B7 0 B6 1 B5 * B4 * B3 DS3 B2 DS2 B1 DS1 B0 DS0 *:don't care
ND
SERIAL DATA FOR THE 2 AND ASCENDING WORDS When the 1st word is the "Display data RAM address", the 2nd and ascending words must be display data. When the 1st word is the "Command register 1 or 2", the 2nd and ascending words are ignored.
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NJU3426
! ABSOLUTE MAXIMAM RATINGS
PARAMETER Operation voltage Input voltage VFD driving voltage "H" level output current SYMBOL VDD VIN VFDP IOH1 IOH2 RATINGS -0.3 to +7.0 -0.3 to VDD+0.3 VDD-45 to VDD+0.3 -15 -35 UNIT V V V mA mA (VSS=0V, Ta=25C) CONDITIONS
"H" level -100 mA IOH Total output current "L" level output current IOL 20 mA "L" level All output pins 100 mA IOL Total output current Operating temperature Topr -40 to 85 C Storage temperature Tstg -55 to 125 C Power dissipation PD T.B.D. mW QFP Note 1): The LSI must be used inside of the "Absolute maximum ratings". Otherwise, an electrical or physical stress may cause permanent damage to the LSI. Note 2): De-coupling capacitors for VDD and VSS and VFDP and VSS must be connected for stabble operation. Note 3): The following voltage relation must be maintained; VDD> VSS VFDP, VSS=0.
Relative to VDD. 1 pin out of S0 to S15 pins 1 pin out of T0 to T13 pins All output pins
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NJU3426
! ELECTRICAL CHARACTERISTICS
*
DC characteristics 1 (VDD=5.0V, VSS=0V, Ta=-40 to 85C) MIN TYP MAX UNIT 4.5 5.5 V 0.8VDD V 0.2VDD 1 -7 -15 140 70 200 120 260 200 A mA mA k k
CONDITIONS PARAMETER SYMBOL Operating voltage VDD VDD terminal XT, RSTb, CSb, SCK, SI terminals "H" level input voltage VIH "L" level input voltage VIL CSb, SCK, SI terminals Input off leak current IIZ VDD=5.5V, VI=0 or 5.5V SO to S15 VDD=4.5V, terminals VFDP=VDD-40V, Display output current IOH VOH=VDD-2.5V TO to T13 terminals RSTb terminal, Ta=25C Pull-Up resistance RUR VDD=5.0V, VI=VSS S0 to S15, T0 to T13 terminals, Ta=25C Pull-down resistance RDST VDD=5.0V, VI=VSS, VFDP=VDD-40V VFDP terminal VDD=5.0V, VFDP=VDD-40V, Display operating IDD current Ceramic resonator:1MHz, All Segment/Timing output ON
10
15
mA
*
DC characteristics 1 SYMBOL fXT, fCL tCLH, tCLL tSIS tSIH fSCK tSCI tRSTb tR CONDITIONS Fig. 1 Fig. 1 Fig. 2 Fig. 2 Fig. 3 Fig. 3 Fig. 4 Fig. 5 60 10 1.5 10 10 0.05 (VDD=5.0V, VSS=0V, Ta=-40 to 85C) MIN TYP MAX UNIT 0.8 3.5 20 MHZ ns ns ns MHZ s s ms
PARAMETER Operating oscillation frequency, External clock Input External clock Input Rise time, Fall time Serial input data setup time Serial input data hold time Serial clock frequency Serial clock interval time Reset palse width Power rise time
10
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NJU3426
*
DC characteristics 2 (VDD=3.3V, VSS=0V, Ta=-40 to 85C) MIN TYP MAX UNIT 3.0 3.6 V 0.8VDD V 0.2VDD 1 -2.2 -5.5 140 70 200 120 260 200 A mA mA k k
PARAMETER SYMBOL CONDITIONS Operating voltage VDD VDD terminal XT, RSTb, CSb, SCK, SI terminals "H" level input voltage VIH "L" level input voltage VIL CSb, SCK, SI terminals Input off leak current IIZ VDD=3.6V, VI=0 or 3.6V VDD=3.0V, S0 to S15 terminals VFDP=VDD-40V, Display output current IOH VOH=VDD-1.5V T0 to T13 terminals RSTb terminal, Ta=25C Pull-Up resistance RUR VDD=3.0V, VI=VSS S0 to S15, T0 to T13 terminals, Ta=25C Pull-down resistance RDST VDD=3.0V, VI=VSS, VFDP=VDD-40V VFDP terminal VDD=3.3V, VFDP=VDD-40V, Display operating IDD Ceramic resonator:1MHz, current All Segment/Timing output ON
10
15
mA
*
AC characteristics 2 SYMBOL fXT, fCL tCLH, tCLL tSIS tSIH fSCK tSCI tRSTb tR CONDITIONS Fig. 1 Fig. 1 Fig. 2 Fig. 2 Fig. 3 Fig. 3 Fig. 4 Fig. 5 120 20 0.8 10 20 0.05 (VDD=3.3V, VSS=0V, Ta=-40 to 85C) MIN TYP MAX UNIT 0.8 2 20 MHZ ns ns ns MHZ s s ms
PARAMETER Operating oscillation frequency, External clock Input External clock Input Rise time, Fall time Serial input data setup time Serial input data hold time Serial clock frequency Serial clock interval time Reset palse width Power rise time
5
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NJU3426
fXT, fCL VIH XT, XTb VIL VIL VIH VIH
tCLH
tCLL Fig. 1
VIH SCK VIL tSIS SI VIH VIL Fig. 2 CSb 50% 50% tSIH VIH VIL
SCK
50%
50%
50%
tSCI
fSCK
tSCI
tSCI
Fig. 3 tRSTb RSTb VIL VIL
Fig. 4 tR 90% VDD 10% Fig. 5
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NJU3426
! APPLICATION CIRCUIT
N.C.
N.C.
N.C. N.C.
VFDP N.C. RSTb
MPU
CSb SCK SI VSS
NJU3426FP1
C1 C0 VDD
C2
XT XTb N.C. N.C. S4 S5 S6 S7 S9 N.C. VDD S0 S1 S2 S3 S8
VFD
N.C.
T13
T12
T11
T10
T9
T8
T7
T6
T5
T4
VFDP
T3 T2 T1 T0 S15 S14 S13 S12 S11
S10
[CAUTION] The specifications on on this databook are only The specifications this databook are only given for information without any guarantee given for information , , without any guarantee as regards either mistakes or omissions. asregards either mistakes or omissions. The The application circuits in this databook applicationcircuits in this databook areare described only to show representative usages described only to show representative usages of the product and not intended for for the the product and not intended the guarantee or permission of of any right including guarantee or permission any right including the industrial rights. the industrial rights.
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